Security News

Hot fuzz: Cascade finds dozens of RISC-V chip bugs using random data storm
2023-10-24 21:41

Unlike other CPU fuzzers, Cascade can construct long random programs that manage the control flow during execution. What separates Cascade from similar tools is that it relies on a technique called asymmetric ISA pre-simulation.

RISC-V Soft CPU Contest challenges designers to develop a hardware secure RISC-V soft CPU solution
2019-07-17 01:30

The RISC-V Foundation, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), announced the...

Hex Five and wolfSSL launch a secure IoT stack for RISC-V
2019-02-26 23:45

wolfSSL, a leading provider of TLS cryptography and Hex Five Security, provider of MultiZone Security, the first Trusted Execution Environment for RISC-V announce general availability of the...

Arms race: SiFive, Hex Five build code safe houses for RISC-V chips
2018-09-10 20:08

Those developing custom CPUs can now tap a TrustZone-ish trusted execution environment If you've been looking at SiFive's RISC-V-based chip technology and thinking, y'know what, it's missing an...

Boffins trying to build a open source secure enclave on RISC-V
2018-08-31 23:57

Open source trusted execution component expected this fall At some point this fall, a team of researchers from MIT's CSAIL and UC Berkeley's EECS aim to deliver an initial version of an open...

Brains behind seL4 secure microkernel begin RISC-V chip port
2018-04-23 05:02

Unveil first code, joins giants in industry standard-club Last week, the first RISC-V port of its seL4 microkernel was released by the Data61 division of the Australian government's Commonwealth...

Brains behind iOS' secure microkernel start moving it to RISC-V
2018-04-23 05:02

Unveil first code, joins giants in industry standard-club Last week, the Data61 division of Australia's Commonwealth Scientific and Industrial Research Organisation (CSIRO) released the first...