Security News > 2021 > March > Synopsys launches IP solution for PCI Express 6.0

Synopsys announced complete IP solution for the PCI Express 6.0 technology that includes controller, PHY and verification IP, enabling early development of PCIe 6.0 system-on-chip designs.

Built on Synopsys' widely deployed and silicon-proven DesignWare IP for PCIe 5.0, the new DesignWare IP for PCIe 6.0 supports the latest features in the standard specification including, 64 GT/s PAM-4 signaling, FLIT mode and L0p power state.

To achieve the lowest latency with maximum throughput for all transfer sizes, the DesignWare Controller for PCI Express 6.0 utilizes a MultiStream architecture, delivering up to 2X the performance of a single-stream design.

"Advanced cloud computing, storage and machine learning applications are transferring significant amounts of data, requiring designers to incorporate the latest high-speed interfaces with minimal latency to meet the bandwidth demands of these systems," said John Koeter, senior vice president of marketing and strategy for IP at Synopsys.

"With Synopsys' complete DesignWare IP solution for PCI Express 6.0, companies can get an early start on their PCIe 6.0-based designs and leverage Synopsys' proven expertise and established leadership in PCI Express to accelerate their path to silicon success."

"Synopsys' latest DesignWare IP for PCIe 6.0 is a leading indicator of the global ecosystems' ongoing commitment to this important industry standard and sets the stage for PCIe Gen 6 development and adoption on future Intel platforms."

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