Security News > 2021 > May > Cadence unveiled its third-generation 112G long-reach (112G-LR) SerDes IP on TSMC’s N5 process

Cadence Design Systems unveiled its third-generation 112G long-reach SerDes IP on TSMC's N5 process for hyperscale ASICs, artificial intelligence/machine learning accelerators, and switch fabric systems on chip.

The Cadence 112G-LR PAM4 SerDes IP on TSMC's N5 process delivers the power, performance and area efficiency required to build the high-bandwidth and high-reliability products for next-generation cloud data centers.

Through various 112G-LR SerDes design wins and deep collaborations with leading hyperscale and data center customers, Cadence has incorporated specific enhancements in the third-generation product and currently has N5 test chips in-house that are undergoing characterization.

"Our next-generation 112G-LR SerDes on TSMC N5 solution offers 25% power savings, 40% area reduction and better design margins over the previous generation," said Sanjive Agarwala, corporate vice president and general manager of the IP Group at Cadence.

"Our close collaborations with leading hyperscale and data center customers have given us the insights into the stringent industry requirements, resulting in a new design with enhanced architecture that offers improvements on all the key parameters for 112G SerDes and network switches. Our 112G-LR SerDes solution on TSMC's N5 process further solidifies our leadership position with high-performance connectivity IP offerings for hyperscale data centers, and customers can also enjoy the benefits associated with the TSMC N5 process technology."

The 112G-LR SerDes IP on TSMC's N5 process is part of the broader Cadence IP portfolio and supports the Cadence Intelligent System Design strategy, which enables advanced-node SoC design excellence.

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