Security News > 2020 > October > Cadence System VIP: Automating SoC testbench assembly, bus and CPU traffic generation

Cadence System VIP: Automating SoC testbench assembly, bus and CPU traffic generation
2020-10-14 01:30

Cadence Design Systems announced Cadence System-Level Verification IP, a new suite of tools and libraries for automating system-on-chip testbench assembly, bus and CPU traffic generation, cache-coherency validation and system performance bottleneck analysis.

Using Cadence System VIP, customers creating complex hyperscale, automotive, mobile and consumer chips can improve chip-level verification efficiency by up to 10X. The new Cadence System VIP solution takes Cadence's market leadership in IP-level verification automation and brings it to the chip level.

"By using Cadence System Traffic Libraries and System Performance Analyzers, Arm was able to automate complex test generation processes, enabling a quicker PCIe integration verification and performance analysis."

"Our new Cadence System VIP solution dramatically improves verification throughput by automating some of today's most critical labor-intensive chip-level verification challenges."

The Cadence System VIP tool suite is part of the broader Cadence Verification Suite and supports the company's Intelligent System Design strategy.


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