Security News > 2020 > August > OpenFive launches D2D interface IP portfolio for HPC and chiplet markets

OpenFive announced the launch of a new Die-to-Die interface IP portfolio to serve next-generation chiplet based designs for networking, HPC, and AI markets.

OpenFive Die-to-Die IP is intended to enable SoC architects to connect chip logic to optimized XSR/VSR/SR based SerDes while embracing native customer-defined interfaces, or Arm AMBA AXI. OpenFive's die-to-die controller uniquely offers low latency and scalable throughput to address very high-bandwidth requirements in the multi terabits range with a single controller.

OpenFive is uniquely positioned with over a decade of experience in providing solutions for leading networking, storage, and AI products with its Interlaken IP for Chip-to-Chip connectivity, coupled with 2.5D-based ASIC integration experience for HBM2E based products.

OpenFive will continue to extend the series of Die-to-Die IP portfolio for other parallel PHY based architectures in the future as they become available.

The OpenFive portfolio includes low-latency, high-throughput Interlaken connectivity fabric, 400/800G Ethernet, High-bandwidth memory, USB subsystem IP, and die-to-die interconnect IP for next-generation heterogeneous chiplet-style products.

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